The present invention relates to process and structure for capacitor elements on integrated circuit chips. In particular, the present invention provides capacitor elements having high capacitance per unit area and stable capacitance with variations in applied voltage which are compatible with CMOS chips. No additional process steps are required to fabricate capacitor elements according to the present invention.
In integrated circuit design, on-chip capacitors are frequently required. Such capacitors, to be optionally useful, must have high capacitance per unit area and a capacitance value that does not change with variation in the voltage applied to the capacitor. Where such characteristics have been produced, additional processing steps are usually required.
A conventional CMOS capacitive element 10 is shown in FIG. 1. Such elements are typically located apart from other elements on the chip. Furthermore, at least one additional process step is required to form oxide layer 13 over N+ diffused region 12 in N-well 11 to insulate electrode 14 from electrode 15.
Other prior art semiconductor chip capacitors which are formed without additional process steps usually have at least one semiconductor plate. See for example, U.S. Pat. No. 4,384,218, which describes a prior art MOS capacitor having only one polysilicon plate while the other plate comprises semiconductor regions in the substrate. Similarly, see also U.S. Pat. Nos. 4,216,451, 4,536,947, 4,559,548 and 4,570,331. Such capacitors are notorious for instability of capacitance with variations in applied voltage.